SEMI Northeast Forum: Power Electronics Manufacturing - From Concept to Production

By Paul Werbaneth, Intevac, Inc.

Great things are happening in New York State, as I learned recently while attending the SEMI (www.semi.org) Northeast Forum on Power Electronics Manufacturing in Albany, New York.

The audience that filled the room at SUNY Polytechnic Institute's College of Nanoscale Science and Engineering (SUNY Poly CNSE) on September 30 heard from five speakers presenting on the topic of power electronics manufacturing in a program that flowed from the big picture (Paul Farrar, GM, New York Power Electronics Consortium) through to business focus (Peter Sandvik, Product Manager, SiC Business Unit, GE) all the way to supply chain (Scott Balaguer, Edwards; Somit Joshi, Veeco; Dr. Fulvio Mazzamuto, SCREEN-LASSE).

In his remarks to the Forum, Paul Farrar explained that the New York Power Electronics Manufacturing Consortium (NY-PEMC) is a public-private partnership that will help, together with founding member GE, develop the next generation of SiC-based power electronics at SUNY’s 150mm SiC  wafer fab.

Full house at the SEMI Northeast Forum on September 30, 2015 at SUNY Polytechnic Institute at CNSE in Albany New York.

Why silicon carbide?  The thinking at NY-PEMC, said Farrar, is that higher maximum operating temperatures than silicon-based power devices, reduced power losses, higher power densities, and more reliable operations in high temperature environments, some of the notable characteristics SiC-based devices offer, make for a compelling value proposition worth developing. 

The commercial markets where SiC power electronics will likely find welcome homes include hybrid vehicles, medical imaging, aircraft, and renewable energy (solar, wind).

Details about the PEMC SiC fab at SUNY Poly include: the active team comprises both GE and CNSE staff members and engineers; the team is working to establish a 10,000 to 15,000 wafers-per-year SiC production facility; the working tool set is based on 200mm processing equipment, specially configured for 150mm SiC wafers. 

Generally speaking, the feature size/lithography requirements for the SiC process are on the order of 0.25µm; beyond photolithography systems, the tool set includes the usual suspects – RIE, metallization, diffusion furnaces, implant, and metrology.  Tool orders have already been let, with equipment arriving and being installed now through 1H 2016.

Working silicon carbide is expected to be delivered in 2H 2016.

NY-PEMC is actively accepting new members, and New York State is offering generous encouragements to new and expanding businesses, and companies are encouraged to participate if they at all see SiC in their future.

AGV transporting a pod of wafers between two of the buildings (NanoFab North to NanoFab Xtension [sic]) at the College of Nanoscale Science and Engineering. 

Banner at CNSE where SEMI Northeast Forum was held. From left, Dr. Nancy Zimpher, Chancellor, State University of New York; President Barack Obama; Dr. Alain Kaloyeros, founding president and CEO, SUNY Polytechnic Institute; and New York State Governor Andrew Cuomo.   

GE certainly sees SiC in its future, having already seen silicon carbide in its past.  As Peter Sandvik pointed out, GE has a 20+ year history with SiC-based devices, starting from its work employing SiC UVphotodiodes for combustion studies performed more than 20 years ago, to its subsequent work with 4” SiC wafers in order to produce power MOSFETs demonstrating stable operation at 200°C. 

In the markets in which GE sees a SiC future, namely aircraft power systems, wind and PV converters, and electric propulsion, among others, the higher cost of a silicon carbide power device over its silicon brethren is outweighed by balance-of-system benefits.

Among these balance-of-system benefits are the lower overall system costs, and the smaller size and lower weight of SiC-enabled PV inverters, advantages obtained as a result of SiC devices being able to operate at higher voltages than can silicon, thus allowing for simpler system topologies.  The naturally higher efficiency of a SiC-based inverter results in lower operating costs, and the resultant decrease in waste heat, along with the higher operating temperature margin for SiC power electronics, means a lower-cost thermal management solution for the inverter.

GE understands that using a somewhat more expensive component, the SiC MOSFET, substantially reduces the PV inverter balance-of-system costs.  Everybody wins ─ it’s better living through technology, as a result of imagination at work, and the same value proposition applies to a wide range of products and markets.

The electronics industry supply chain corridor in New York State covered by Edwards (now part of the Atlas Copco Group) starts in the west, in Buffalo (on Lake Erie), moves horizontally from there over to Rochester, Syracuse, and Utica (the Erie Canal path), carries on east until it takes a quick look up at Malta, and then bends south to Albany and Fishkill (following the Hudson River).   Along the way Edwards serves the PV industry, photonics, GaN power electronics, nano, SiC power electronics, and CMOS IC. 

From 1825, when the Erie Canal first opened, to almost 200 years later, today, the same basic route bargemen plied is still a high-tech corridor.

Under the “Single Vendor”-model, Scott Balaguer’s organization at Edwards operates as the one-stop-shop for abatement systems, vacuum equipment, and pipe-work and temperature management systems, performing both hook-up / installations and long-term warranty and service support for its customers.

The ‘Green Mode’ capable pumps and abatement systems allow for reduced utility usage during fab idle periods, saving both money and the earth, in the form of reduced CO2 emissions.

Yield and Productivity are the two major cost drivers of the epitaxial depositions required for both GaN and SiC device fabrication, and Veeco is working on both drivers for both materials, as was heard in the presentation given by Somit Joshi.

Just as silicon epitaxial technology went from the batch reactor stage to the single-wafer reactor stage in order to produce better device yields, and then went to the cluster tool stage for better productivity, so too has epi for GaN and for SiC evolved on a similar path.

Add Continuous Improvement Projects along the way and you arrive having better uniformity, better run-to-run control, lower particles, higher good wafers out, and lower consumables in commercial epi systems, which are just the attributes needed to help reduce manufacturing costs for SiC device manufacturing, along with reducing the manufacturing costs of other wide bandgap materials.

Another appealing new process technology from a fab perspective is UV Laser Annealing for SiC manufacturing processes, the subject of Fulvio Mazzamuto’s talk.  UV laser annealing of SiC wafers enables crystal defect “repair” and also the activation of high dose implants, and it has the advantage of being compatible with BEOL processing, where temperature budgets can be tight.  The ultra-fast non-equilibrium laser annealing can produce very high (>3,000°C) localized zones of elevated temperature, and could be one of the new process techniques that will give a boost to SiC device and manufacturing maturity, making SiC potentially that much more competitive with silicon-based power devices.

Great things are indeed happening in New York State, and SEMI, along with the five speakers in the recent Northeast Forum, want that known.

Upcoming SEMI events include SEMICON Japan 2015 (December 16-18) and Industry Strategy Symposium 2016 (January 10-13).  For addition information on upcoming SEMI events, click here.

Website: http://www.semi.org/en/node/59231?id=semiblog

[Note: A slightly different version of this piece originally appeared at 3D InCites / 3D+.]